# Based on CPLD / FPGA design of semi-integer frequency divider

CPLD (Complex programmable Logic Device, complex programmable logic devices) and FPGA (Field programmable Gates Array, field programmable gate array) are programmable logic devices, which are in PAL, GAL and other logic developed on the basis of. With the past, PAL, GAL, compared, FPGA / CPLD relatively large size, suitable for timing, and combination logic circuit applications. It can replace dozens or even hundreds of blocks of common IC chip. This chip is programmable and easy to achieve the program changes and so on. Since the connection of chip hardware description can be stored on disk, ROM, PROM, or EPROM in which the programmable gate array chip and external circuitry to remain intact in the case, for an EPROM chip, can achieve a new function. Ta has the design development cycle short, design and manufacture of low cost, Kaifagongju advanced, Biaozhun product Wuxu test, stability of quality and Shi Shi Zai Jian Yan, etc. You Dian, therefore can be widely used Chanpin the Yuan Li Zhizhong design and product production. Almost all applications gate array, PLD, and small and medium-scale Universal application of digital integrated circuits may be occasions FPGA and CPLD devices.

Based on CPLD / FPGA design of semi-integer frequency divider

In modern electronic systems, digital systems share is growing. The more potential system development and integration of digital technology, while the CPLD / FPGA as a programmable ASIC (application specific integrated circuit) devices, digital logic system, it will play an increasingly important role.

In the digital logic circuit design, the divider is a basic circuit. Usually used to carry out a given frequency divider to obtain the required frequency. Integer divider implementation is very simple, can use standard counters can also be designed and implemented using programmable logic devices. However, in some cases, the clock source and not a multiple of the desired frequency relationship between the fractional divider can be used at this time divide. For example: frequency factor of 2.5,3.5, 7.5 and other semi-integer divider. The author in the analog design frequency meter pulse signal, with a half-integer divider on this circuit. As the clock signal is 50MHz, the circuit needs to generate a 20MHz clock signal, the frequency division ratio of 2.5, the integer frequency will not be competent. To solve this problem, I use VIDL hardware description language and schematic way, by MAX + plus II development software and the ALTERA's FLEX family of EPF10K10LC84-4 based FPGA easily completed the half-integer frequency divider circuit.

2, the basic principle of fractional frequency

The basic principle of fractional frequency pulse stimulation is used the first counter and PLL design two different frequency than the integer divider, and then by controlling the frequency per unit time than the emergence of two different times to obtain the required fractional value. Such as the design of a frequency divider factor of 10.1, the divider can be designed to divide 9 10, 1 11 frequency, so the total frequency value:

F = (9 × 10 +1 × 11) / (9 +1) = 10.1

Implementation of features from this can be seen, because the value of crossover frequency changing, so the signal obtained by frequency jitter greater. When the frequency division factor of N-0.5 (N is an integer), net pulse time can be controlled in order to make the output into a stable pulse frequency, not an N divider, the first N-1 frequency.

Based on CPLD / FPGA design of semi-integer frequency divider

3 circuit

Frequency division factor of N-0.5 of the divider circuit may be an XOR gate, a counter module and a second divider N composition. In the realization, the modulus N counter can be designed with a preset counter, it can achieve any frequency division factor of N-0.5 divider. Figure 1 shows the general half-integer frequency divider circuit.

Using VHDL hardware description language that can implement any model N of the counter (whose operating frequency can reach 160MHz and above), and can cause mold N logic circuits. After using schematic way N-mode logic circuits, XOR gates and D flip-flop connected, can achieve a half integer (N-0.5) crossover and (2N-1) sub-frequency.

4 half-integer frequency divider design

Is through the design of a frequency division factor of divider 2.5 FPGA design is given with the general method of half-integer divider. 2.5 divider of the module 3 by the counter, XOR gates and D flip-flop.

Based on CPLD / FPGA design of semi-integer frequency divider

4.1 Counter Mode 3

The counter can generate a frequency division factor of 3 divider, and generates a default logical symbols COUNTER3. The input port RESET, EN and CLK; output port for the QA and QB. Here are 3 counter VHDL model description of the code:

library ieee;

use ieee.std-logic-1164.all;

use ieee.std-logic-unsigned.all;

entity counter3 is

port (clk, reset, en: in std-logic;

qa, qb: out std-logic);

end counter3;

architecture behavior of counter3 is

signal count: std-logic-vector (1 downto 0);

begin

process (reset, clk)

begin

if reset = '1 'then

count (1 downto 0) <= "00";

else

if (clk 'event and clk = '1') then

if (en = '1 ') then

if (count = "10") then

count <= "00";

else

count <= count +1;

end if;

end if;

end if;

end if;

end process;

qa <= count (0);

qb <= count (1);

end behavior;

Arbitrary modulus counter and mode 3, the description of the structure identical to the counter, the counter is just a different number of states. After compiling the above procedure, timing simulation, available in the MAX + PLUS II simulation waveform shown in Figure 2.

Based on CPLD / FPGA design of semi-integer frequency divider

4.2 The complete circuit and waveform simulation

Will COUNTER3, XOR gates and D flip-flop circuit shown in Figure 3 through logical connections and, with schematic input transferred graphics editor, and then by the logic synthesis can be simulated waveform shown in Figure 4. The figure outclk and inclk waveform can be seen, outclk will inclk cycle every 2.5 to generate a rising edge of the Department to achieve the frequency division factor of 2.5 divider. Set inclk is 50MHz, the outclk as 20MHz. We can see that the circuit is not only available frequency coefficient is 2.5 crossover (outclk), but also by frequency division factor of 5 of the divider (Q1).

5 Conclusion

ALTERA FLEX family of companies selected EPF10K10LC84-4 based FPGA devices to achieve half-integer frequency, the post-adaptation by the logic synthesis results as listed in Table 1. In this case the counter is 2-bit wide bit vector, that is, frequency division factor of four within a half integer value. If the frequency coefficient of greater than 4, you need to increase the count of the bit width.

Table 1 Analysis of half-integer frequency divider results fit

Use the device I / O delay time using the pin number of the operating frequency

EPF10K10LC844 17.7ns 5 / 84 (5.95%) 68.02MHz