FPGA-based design and implementation of multi-frequency

Divider is used in FPGA design the basic unit of frequency is very high one. Although most of the design also widely used integrated phase-locked loop (such as altera the PLL, Xilinx's DLL) to carry out clock frequency, and phase shift multiplier design, but with less stringent requirements for the design of the clock, through the Independent design of the clock frequency of the realization is still very popular. First, this method can save PLL resources Moreover, this approach consumes much of the logic cells can achieve the purpose of the clock operation.

1 integer Divider

Dual frequency 1.1 times

Implementation of even very simple divider, counting by the counter is entirely achievable. In case of an even number N times the frequency, it can be divided by the frequency of the clock trigger counter count when the counter counts from 0 to N/2-1, the output clock flip, and a reset signal to the counter to make the next a clock counting from zero. This cycle, you can even achieve any frequency. Figure 1 shows the duty cycle of 36 points for the 1:1 frequency of the simulation waveforms.

FPGA-based design and implementation of multi-frequency

Odd frequency 1.2 times

There are two odd multiple divider realization, one can be achieved through the counter, such as for third frequency, can be divided by frequency clock rising edge triggered counter to count for model 3, when the counter counts to a value close to turning twice. Example, in the counter counts to 1, the output clock flip, count to 2 flip again. Thus, on count 1 and 2 were close to two flip. So we realized the third frequency, the duty cycle of 1 / 3 or 2 / 3.

Duty cycle 1 / 15 of the 15 sub-frequency design of the main code is as follows:

FPGA-based design and implementation of multi-frequency

If you want to achieve a 50% duty cycle for the third-frequency clock, the clock frequency may be falling through the trigger count and to count the same way and rising to third frequency, and then generate the third frequency on the falling edge rising edge clock and generated clock phase or operation. 50% duty cycle can be obtained by third-frequency clock divider is the third odd way. This method can achieve any odd frequency. If its classified as a general approach: For 50% duty cycle to achieve N times the odd frequency, we must first carry out the rising edge of trigger for mode N counting, counting to a certain value selected to conduct the output clock flip , and then through (N-1) / 2 flip again, you can get a 50% duty cycle odd n non-frequency clock. Falling again at the same time trigger mode N count, when it reaches the output clock with the rising edge triggered flip the selected value is the same, and then to output the clock turn, the same, after (N-1) / 2, the output clock again turn to generate 50% duty cycle odd n non-frequency clock. 50% duty cycle of these two non-n-clock phase or frequency division operation, you can get 50% duty cycle odd n clock frequency. Figure 2 shows the duty cycle of 1:1 3 fraction frequency circuit schematic. Figure 3 for simulation waveform.

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