Serial Peripheral Interface (SPI) of the CAN bus isolation extended design

I. Introduction

CAN bus is an effective support for distributed control and real-time control of serial data communication protocol, it is a multi-master bus, the network nodes can be any one of its own initiative at any time other nodes on the network to send information, regardless of master and slave, the priority between the node points, which means of communication and flexible; CAN may point to point, one-to-multipoint (group), and global broadcast and other ways to send and receive data; CAN non-destructive bit arbitration technique, priority send, you can greatly reduce the time the bus arbitration of conflict, in a good performance under heavy load performance.

Serial Peripheral Interface (SPI) of the CAN bus isolation extended design

CAN on the actual number of nodes up to 110, the communication medium can be twisted pair, coaxial cable or optical fiber, direct communication distances of up to 10km (transmission rate 5kbps); maximum communication speed up to 1Mbps (transmission distance to 40m). CAN protocol is the abolition of one of the greatest features of the traditional station address code, and replace the data block to encode communications, CAN data link layer frame structure with a short, each frame is 8 bytes, easy error correction. Industrial areas to meet the usual control commands, work status and the general requirements of test data. Meanwhile, the 8 bytes will not take the bus for too long, thus ensuring real-time communication.

CAN bus has a strong error correction capability, each frame has a CRC checksum and other information error detection measures to effectively reduce the data error rate. CAN node in the error serious cases, with automatic shut down function, so that other nodes on the bus is not affected. Support the differential transceiver, thus suitable for high-jamming environment.

We designed a CAN bus master from the communication control system shown in Figure 1, the control system inside and outside the control of two separate forms of CAN network to the main console to send commands and data, through the master-slave communication module and from the CAN network node communication subsystem control units on data acquisition and control. This system enables CAN bus nodes increased n times; CAN bus transmission rate and communication range greatly increased; also significantly enhanced anti-jamming capability.

This article discusses the main CAN bus communication control system from the master-slave communication module hardware and software design and implementation methods. Master-slave communication module of the console and the control unit from the CAN network data communications between the isolated extension of the communication data processing, transmission and control of CAN networks have some reference.

Second, the hardware design

Serial Peripheral Interface (SPI) of the CAN bus isolation extended design

Master-slave communication module control block diagram shown in Figure 2, the core chip is the TI TMS320C2000 family of companies in the digital control for a DSP. It includes a single chip 10-bit ADC, on-chip flash program memory, event management, digital input and output I / O port, etc.. In order to facilitate communication with various peripheral devices, DSP also provides some interfaces: CAN interface, serial peripheral interface (SPI), serial communication interface (SCI) and so on. Which, SPI interface is the industry standard synchronous serial interface, is a full-duplex, three-wire communications systems. It allows the DSP with a variety of peripheral devices to the serial method (can be configured as a 16-bit data while simultaneously sent and received) to communicate. In the SPI interface, the data transmission needs of a clock signal and two data lines. SPI can operate in master mode or slave mode. In the main mode, each data send / receive function requires a second clock; in from the model, each data clock signals are received only after the send / receive.

3, SPI works

1) SPI signal description

Communication control part of the Figure 2 diagram, two DSP chips use four wire direct SPI interface: serial clock line (SPICLK), the main chip input / output data lines from the film SPISOMI, the main chip output / input data line from the film SPISIMO and active-low chip select lines from SPISTE.

SPICLK is the main piece of the clock line, for the MISO data to send and receive clock signal provides synchronization. Each data transmission needs 1 clock function, and thus to send or receive a byte of data needs 1 to 16 clock effect. The clock is the main piece of hardware through the main film set, and and from the film SPICLK connected.
MISO is the main piece of input / output data lines from the film. The main piece of the MISO MISO should be connected from the film were high in the former data exchange. MOSI is the master SPI SPI interface chip output / input data from the chip pin. This pin should be connected to the main piece of data output and data input from the film MOSI, were high in the former data exchange.

SPISTE only way for LOW is selected from the from the film, the main piece SPISTE corresponding pin is configured as I / O port as from the film SPI chip select input pin.

Serial Peripheral Interface (SPI) of the CAN bus isolation extended design

2) the main mode

Can simultaneously send and receive work in the main mode. The salient features of the main mode is either sent or received always SPICLK signal, sending operation is to SPIDAT (or SPITXBUF) write data triggered. In the main mode, the role of the clock signal 1 corresponds to a data transmission (M0SI) and another data reception (MISO). Shown in Figure 3, in the main film data from the shift register issued from left to right sent from the film (MOSI), while the data from a film made from right to left into the main piece (MISO), after 16 clock cycles to complete a byte to send. Input bytes remain in the shift register, then SPI INT FLAG bit automatically set bit (if interrupt settings, then generate an interrupt), the shift register data will be latched to the SPIRXBUF, the subsequent read operation on SPIRXBUF the data read out.

3) From the model

Send and receive work simultaneously from the mode. The salient features from the model are: whether sending or receiving the signal must always be under the effect of the SPICLK and SPISTE signal must be valid. When SPISTE signal fails, the data sent and enter the data can not be regarded as invalid. This is because the input clock signal is the logical and operation with SPICLK, but SPICLK signal is SPISTE reversal. So that when SPISTE is high, there is no clock signal input. Send and receive data, the process of Figure 3 shows, similar to the main mode, only the data out shift register and enter the opposite direction.
4, software design

SPI communication with a CAN message sent 5 bytes as a unit of information exchange. Main chip control SPICLK signal can start at any one time packet transmission; from the film before sending the packet through the port line to the main chip to send an external interrupt request, the request success Houzhu chip output SPICLK signal to start from the film packet transmission. SPI interrupt from the film in major film to receive the message sent to; the main piece to complete the external interrupt reception of messages from the film. When the main piece and the film also has a message from the transmission, the system first major film packet transmission, and then send packets from the film.

1, the main chip to send, to receive messages from the film

The main chip to send messages, receiving messages from the chip software flow chart shown in Figure 4. The main chip to send a message from the film before the prohibition of the external interrupt, which is prohibited to send messages from the film. CAN transmit buffer and then take a message to send into the SPI register in, and then send the register from the SPI data were obtained from a byte write SPITXBUF start SPISIMO register data pins to send the same time, SPI interrupt from the piece started to receive a response to the main piece of data is sent, when a byte received from the film after triggering the main line through the mouth piece of XINT1 external interrupt to inform the main piece of data has been received, the main piece to respond to this XINT1 external After the break, and then send the next byte of data, when a packet transmission is completed, the main piece to the external interrupt is enabled to receive messages. End message received from the film after the completion flag set to receive messages to CPU for packet processing.

Serial Peripheral Interface (SPI) of the CAN bus isolation extended design

2, sent from the film, the main piece to receive messages

Send a message from the film, the main piece to receive messages software flowchart in Figure 5. From the film in sending messages, through a port line to the main chip to send a XINT1 external interrupt request packets to send, when the main piece to respond to this disruption, send a pseudo-data (such as # 0FFFFh) to tell from the film can begin to report send text from the test piece to the request packet receiving flag is set, then send the buffer from the CAN take a message to send into the SPI register in, and then send the register from the SPI, fetch a byte Data written to SPITXBUF register, through the mouth piece to the main line to send XINT1 external interrupts, asking permission to take the data chip, the main piece in the XINT1 interrupt service routine in the monitoring of the interrupt flag is set, the sending false data # 0FFFFh (start data from the chip sent SPICLK clock), then received byte into SPI buffer received from the film in turn will send a message is complete, clear message received flag. Completed a master piece after receiving messages, set message reception complete flag, and exit the external interrupt to CPU for packet processing.

Serial Peripheral Interface (SPI) of the CAN bus isolation extended design

3, the key technology of processing

CAN bus the transmission of information laws are not random, so I realize with SPI master and slave systems of information transmission must be considered when the data is transmitted from DSP1 to DSP2, we should prohibit the data from DSP2 DSP1 send to the contrary also natural. Otherwise, the data transfer process will be of mutual mistake or lost, affecting the normal operation of CPU. In order to avoid the main message is sent from the process of conflict, the main piece in the XINT1 interrupt service routine to complete a packet to receive, from the film in the SPI interrupt service routine to complete packet reception. During packet transmission, whether the main piece or from the film only when a packet transmission is completed, to proceed to the next frame message transmission. Lord, send the completed from the film every one byte of data, there is a response signal back to flags (see flag meaning) of the judge, in order to confirm whether the integrity of the data sent or received.

As the main chip holds the packet transmission clock signal that the initiative, so the main chip can always send packets. In the message sent from the film, we should first confirm whether the transmission is idle at this time the main piece, if this time the main chip is sending packets, waiting for the main piece from the film will send a complete packet, and then to transmit packets; if the main piece is in idle state transfer from the film can begin to send messages.

V. Conclusion

The CAN bus master from the communication control system plus a number of auxiliary control unit (such as the display control unit, keyboard, etc.) can be used as the main controller from the CAN network using CAN network anomalies in the console does not work, can assist control subsystem operation, the control system design has been applied.

Declined comment

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