CAN bus cyclic redundancy check code and circuit theory

Abstract: In the CAN network to transfer photo paper, the noise disturbance or interruption of transmission and other factors tend to make the receiver received the message error code appears. In order to timely and reliable manner to transmit packets to each other and effectively detect errors, need to adopt error control. Details of the CAN bus error cyclic redundancy check code control principle and implementation method.

In the CAN system to ensure the accuracy of message transmission, the need for error control communication process. The most commonly used method, the feedback re-issued, or upon receipt of error messages issued by the receiver, the sender will automatically resend, this time the error control error detection function only. Error detection code commonly used in two types: parity check codes and cyclic redundancy check code. Parity code is the most common error detection code, and its implementation is simple, but less error detection capability; cyclic redundancy check code encoding is also very simple and low false positives, so to get a communication system wide range of applications. Here CAN networks cyclic redundancy check code (ie, CRC code) of the principle and method.

CAN bus cyclic redundancy check code and circuit theory

1 CRC error detection code works

CRC error detection code is to be processed packet sequence of bits as a binary polynomial A (x) the coefficient, the coefficient divided by the sender and receiver agree in advance a good generator polynomial g (x) after to obtain the remainder P (x) as a CRC check code appended to the text on the original report, and sent with the recipient. Receiver use the same g (x) to remove received packets B (x), if the remainder is equal to p (x), then the transmission is correct (in this case A (x) and B (x) the same); otherwise transfer process in error, re-issued by the sender to re-start CRC checksum, until correct date.

The validation process there are several points to note: ① during CRC calculation, using the binary (modulo 2) algorithms, which do not carry the addition, subtraction did not hesitate bit, its essence is the two operands to XOR logic; ② sent during CRC calculation before the first message expressed by the polynomial A (x) multiplied by xn, where n is generating polynomial g (x) the maximum power value. Multiplication of the binary terms, A (x) · xn is to A (x) shifted left n bits used to store the remainder p (x), it actually sent the message becomes A (x) · xn p (x ); ③ generator polynomial g (x) the first and last coefficient must be 1.

Figure 1 is a CRC check of the working process.

Now there are a variety of generator polynomial is included in the international standards, such as: CRC-4, CRC-12, CRC-16, CCITT-16, CRC-32 and so on. CAN bus used in the generator polynomial is g (x) = x15 x14 x10 x8 x7 x4 x3 1. Can be seen, CANU called line of CRC check polynomial used to verify seven, than CRC checksum (CRC-4, CRC-12, CRC-16, etc.) series (2 ~ 5 ) is much higher, so its error detection ability of a strong, very low false positives, to become effective to improve the quality of data transmission error detection means.

CAN bus cyclic redundancy check code and circuit theory

2 CRC code of the circuit

2.1 Characteristics of hardware

In the CAN bus in order to generate CRC code, the hardware circuit has reset and clock signals in addition to other, but also the participation of the following two control signals: ① fill bit to lift the signal destuff, its effective boolean value is 1; ② CRC test enable signal enable, valid logic 1. The hardware circuit Dete Dian is used selector and replace it with the traditional design using inverse XOR gates, realized Bijiaogongneng also reduce the production costs and also provides engineers with a new design concept of the.

2.2 Hardware Circuit

Figure 2 CRC code shall be to achieve the hardware circuit diagram.

Figure shows the points that need as follows: ① enable signal to lift signal and fills spaces omitted; ② crcnxt represent logic value input packet sequence and the highest bit CRC register XOR the result; ③ grade 0 to 14 as indicated by 15-bit CRC register, rising edge trigger; ④ numbered 1 to 6 as indicated by selector and a combination of logic inverter to realize XOR function, the selector logic function Y = AB AC, the specific structure shown in Figure 3 shown.

2.3 The working process of the circuit

From the above analysis shows: ① When the enable = 0 時, CRC clear 0; ② When the enable = 1, destuff = 1 when calculating the normal CRC; ③ When the enable = 1 and destuff = 0 when the lift is being filled, the data suspended transmission.

In all control signals are valid, the input packets, and each CRC register is the highest bit different and moved after the lowest, while the first 13,9,7,6,3,2 bit registers were and their maximum bit different, or, the results were shifted to the left one; other XOR operation did not register left one bit value, respectively, until each and every packet CRC register are moved up, then register to take the calculated value received CRC code.

If the message bit sequence of length 16, 16 need to be on the left of each message are processed. Ck that if the first k-bit CRC register bit values, Ck 'said the first k bits after shifting bit value (k = 0,1,2,3 ... ... 15), the shift rule in Table 1.

CAN bus cyclic redundancy check code and circuit theory

Table 1 shift rule table

C14 '= C13 ^ crcnxt C13' = 12 C12 '= C11 C11' = C10
C10 '= C9 ^ crcnxt C9' = C8 C8 '= C7 ^ crcnxt C7' = C6 ^ crcnxt
C6 '= C5 C5' = C4 C4 '= C3 ^ crcnxt C3' = C2 ^ crcnxt
C2 '= C1 C1' = C0 C0 '= crcnxt ^ datain

3 CRC checksum of the software

CRC check together with the software is very easy. Given the current information on the methods described in greater use of C language, assembly language to achieve, but the lack of a hardware description language, CRC code given here behavioral Verilog HDL description of the procedure.

Under this program Verilog_XL compile, while successful in the Synopsis on the integrated and optimized.

/ / Code using Verilog HDL to achieve CRC
module crc (clk, rst, enable, destuff, datain, crc);
input clk;
input rst;
input enable;
input destuff;
input datain;
output [14:0] crc;
reg [14:0] crc;
wire crcnxt = datain ^ crc [14];
always @ (posedge rst or posedge clk)
begin
if (rst) crc = 0;
else if (enable & & destuff)
begin
if (crcnxt)
crc <= crc ^ 15h'4599;
else
crc <= (crc [13:0], 1'b0);
end
end
endmodule

CAN bus cyclic redundancy check code and circuit theory

4 Simulation waveform

Assumption is a standard format to send a remote frame, the demand of data bytes is 8, the identifier sequence is 10101011000, then the above process of simulation, the waveform shown in Figure 4. Crc Series 20 starting from the output.

CRC checksum error detection codes are strong, and because of CRC error detection code of software and hardware are simple, they have been widely used in various types of data validation. CRC error detection code to improve data quality, powerful and efficient means of error detection.

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