ARM-based CAN bus intelligent node
Abstract: CAN bus is a widely used real-time field bus is proposed based on ARM7TDMI core with 32-bit micro-controller CAN bus intelligent node design. Details of the ARM control (LPC2294) features, intelligent node structure and system software design, combined with actual on-site hardware anti-interference measures are given.
CAN (Controller Area Network) or Controller Area Network, CAN bus is the most widely used international fieldbus one. It was first introduced by the German company Bosch, CAN communication protocol is an internal measure for automotive components and the implementation of the agreement between the data communication.
As an advanced technology, high reliability, functional, cost and reasonable remote network communication control mode, CAN bus has been widely applied to various automatic control systems. For example, in automotive electronics, automation, intelligent building, electronic systems, security monitoring and other areas, CAN bus has the incomparable advantage. The design of the program are given CAN bus node. It uses built-in multi-CAN bus controller PLC2294 as the main controller, small size makes the node, low power consumption, interference immunity is good, and therefore particularly suitable for automotive, industrial control and medical systems and fault-tolerant maintenance bus.
A hardware design
1.1 LPC2294 features
ARM7 series with ARM7TDMI 32-bit embedded microprocessor cores is very broad application of the embedded RISC processor. The series chip size, low power consumption, low cost, high performance and flexibility, and have more registers, provide expanded enhanced dual 16/32-bit fixed-length instruction set. With 16-bit Thumb instructions can save up to 35% of the space. Also the implementation of water injection line of work also provides embedded ICE2RT logic to support the on-chip breakpoints and debugging point of support, with advanced software development and debugging environment.
ARM-based CAN bus intelligent node
The design firm selected PHILIPS LPC2294 is a powerful new ultra-low power ARM7TDMI core with 32-bit microcontroller. 144-pin package, the two 32-bit timers, Octal 10-bit ADC, four CAN channels and PWM channels and up to nine external interrupt, internal 256K bytes of embedded Flash memory and 16K bytes of high-speed static RAM, including 76 ( use of external memory) to 112 (single) a GPIO port. So rich on-chip resources can meet the needs of industrial control in general, but also can reduce the system hardware design complexity. In addition, LPC2294 JTAG support real-time simulation and tracking, 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code can be up to 60MHz operating frequency of operation.
LPC2294 CAN controller within the integrated four: meet the CAN specification CAN2.0B, ISO 11989-1 standard: Bus Data Port degree can be up to 1Mbps; can access 32-bit register and RAM; global acceptance filter can identify almost all Bus 11-bit and 29-bit Rx identifiers; acceptance criteria for the selection of the filter provides an identifier FullCAN-style automatic reception.
As a core component of this design, LPC2294 only take up the role of the main controller, but also as a CAN network node controller, and other nodes in the network for data transmission and exchange.
1.2 CAN node hardware circuit
CAN node hardware circuit shown in Figure 1, the ARM microcontroller LPC2294, CAN bus transceiver TJA1050T, high-speed optocoupler 6N137 and power isolation module B0505S so on.
Master LPC2294 chip crystal frequency range of 1 ~ 30MHz. The design selected crystal frequency is 20MHz, the VPB divider by setting the internal CPU clock frequency can be improved. 256K bytes of internal high-speed Flash memory for code and data storage. For FLASH memory, built-in serial through the JTAG interface in system programming (ISP), or In-Application Programming (IAP). In order to facilitate debugging and system upgrades can be reserved for those in the design of the interface circuit.
LPC2294 dual power supply. CPU supply voltage range of 1.65 ~ 1.95V (1.8V ± 8.3%), I / O supply voltage range of 3.0 ~ 3.6V (3.3V ± 10%).
Transceiver TJA1050T CAN protocol controller and the physical is the interface between the bus, with "ISO 11898" standard is fully compatible. CANH and CANL ideal match, electromagnetic radiation can be reduced even lower. In addition, TJA1050T no power, the bus showed passive properties, which makes TJA1050T in performance is much better than the previous CAN bus transceiver. TJA1050T There are two operating modes: high-speed mode and silent mode (which by the pin "S" to control). In the high-speed mode, the bus output signal having a fixed slope, and to switch quickly as possible. High-speed mode, for maximum bit rate and maximum bus length of the case, but this time its the smallest transceiver loop delay. Silent mode is forbidden energy transmitter. It does not matter TxD input signal. CAN controller silent mode to prevent uncontrolled congestion caused when network communications.
1.3 Anti-jamming design of hardware
Applied in the design of occasions, produce more electromagnetic signals equipment, including FM equipment, audio equipment, power supply, so anti-jamming device display is particularly important. Taken the following measures:
(1) In order to further enhance the anti-interference ability of CAN-bus node, ensure that all electrical nodes is completely isolated and independent, LPC2294's TX0 and high-speed optocoupler 6N137 RX0 were the TXD to RXD and TJA1050T connected. However, it should be specified that the coupler part of the circuit to be used in two completely separate power supply, or using optocoupler also meaningless. Completely isolated power supply with low power isolated modules B0505S. Although more complex circuits, but increase the stability and security of the node.
(2) CAN bus ends plus two 120Ω resistors, two resistors for the bus impedance matching plays an important role. They will remove the interference of data communication and reliability greatly reduced, if not impossible to communicate.
(3) CANH and CANL and in parallel between the two 30pF capacitors small, you can filter out high frequency noise on the bus and have some ability to prevent electromagnetic radiation; in between two CAN bus access into the terminal the 5.6V of the TVS tube, when the CAN bus fleeing into voltage interference by TVS tube overvoltage protection circuit play a role.
(4) In order to reduce the interference field of the node, useful shielded twisted pair, and based on actual experience, do not need a shielded cable shield grounding.
Software debugging environment using ARM's ARM core processor integrated development tools ADSv1.2. ADSv1.2 integrated assembly, C, C + + compilers and debuggers, compilers, high efficiency, providing a powerful system library to support software debugging, JTAG emulation and debugging hardware debugging. This design uses a JTAG emulation debug.
For the average 32-bit ARM applications, must be initialized before running the main program running environment, namely, the preparation of ARM chip boot code. The boot code includes exception vector table, stack initialization, storage system initialization such as initialization and target board, usually written in assembly language. For this design, the key is to write CAN driver. Main program simply by calling the driver to provide the interface for data receive and transmit, the driver includes four parts: CAN controller initialization, receive data, send data and bus exception handling. Figure 2 was the main program flow chart.
2.1 CAN controller initialization
CAN controller initialization operation including: hardware is enabled, the software reset, equipment, alarm limits, equipment bus baud rate, device interrupt work, equipment acceptance filter works, equipment and other operating mode and start the CAN. Initialization procedure is as follows:
HwEnCAN (CanEum); / / hardware enabled, CanNum = 0 ~ 3, refers to four CAN controllers
SoftRstCAN (CanNum); / / software reset registers
CANEWL (CanNum). Bits.EWL_BIT = USE_EWL_LAN [CanNum]; / / set the error warning limit
CANBTR (CanNum). Word = USE_BTR_CAN [CanNum]; / / initialize the baud rate
VICDefVectAddr = (UINT32) CANIntPrg; / / initialize the interrupt vector interrupt a non-
VICIntEnable 1 = (1 <<19) | (1 <<(20 + CanNum)) | (1 <<26 + CanNum));
CANIER (CanNum). Word = USE_INT_CAL [CanNum];
CANAFMR.Bits.Accbp_bit = 1; / / configure the acceptance filter (bypass state, the acceptance filter mask)
CANMOD (CanNum). Bits.TPM_BIT = USE_TPM_CAN [CanNum]; / / initialization mode
CANMOD (CanNum). Bits.LOM_BIT = USE_MOD_CAN [CanNum];
SoftEnCAN (CanNum); / / Start CAN
LPC2294 on-chip peripherals and pin connection from the pin connecting the module control. CAN controller is enabled by software, hardware devices to control the GPIO registers multiple switches, the specific pin and connect the CAN controller. The CAN registers in the device must be carried out before the software reset, this is because some of CAN registers must be read and write in the soft reset state.
It is worth noting, LPC2294 CAN controller for all the global search function to receive the identifier. 2KRAM can accommodate 1,024 standard identifier or extended identifier 512 or a mixture of two types of identifiers. Software, may set stored in the RAM 1 to 5 form the identifier. CAN controller SJA1000, compared with independent, it can more easily arbitrary complex filter to filter ID, the ID of the receiver to meet the complex filtration requirements. This will undoubtedly greatly reduce the complexity of the system software design and run-time burden. Acceptance filter settings work, you must create a LUT preferred form, the designated start address of each table, with the actual ID address initialize the form. Final acceptance filter mode register set. If the node does not take the initiative to send data, choose the bus into sleep mode when inactive.
2.2 data transmission
Will send the data to be packaged into line with CAN protocol frame format, can be written to send a relief station area, and automatically sent. Figure 3 is sending subroutine flow chart.
Send buffer before writing to inquire about their status. LPC2294 CAN controller in each of the three to send the buffer zone, their status can check CANSR know. Only when there is space in which to send the data buffer that was written. Sending large amounts of data, this step is particularly important, will not guarantee the reliability or send. Start sending successful only through the query CANGSR of TCS-bit or configuration sent successfully interrupt to determine whether the data sent successfully.
ARM-based CAN bus intelligent node
2.3 Data Receiver
Query can be used to receive data mode or interrupt mode. A certain period of time, CAN bus is not always in the activities, in order to improve efficiency, can be used interrupt. In the initialization process must be able to receive interrupts. In the interrupt service routine to read the CANICR, to determine whether to receive interrupt flag, there is data to read receive buffer. Receive buffer data in order to prevent overflow, can open up a loop to receive data queue to temporarily store data, the main program will check the queue to get through the bus data.
2.4 exception handling
Online Bus serious case of failure, CAN nodes may be out of the bus, then the following register bit is set: CANSR the BS bit, CANIR of BEI bit and EI-bit (if enabled) and CANMOD the RM bit. RM CAN controller function will reset and many prohibited. Software the next step must be set to zero RM bit. Send error counter will decrease the release conditions count bus (11 consecutive recessive bits) of section 128 do. Software can read the Tx error counter on the counter to monitor the situation descending count.
In the application, if the previous transmission to the CAN controller's data has not been read out, while the receive buffer has not timely release of information is likely to cause behind the loss. Then must write the command register to clear CANSR data overflow bit. These two exceptions can be handled by interrupt exception, as long as the interrupt handling code can be added subroutine. Other bus exception handling can decide whether the use of software processing.
In short, the software is very important in the preparation and planning. ARM7TDMI RISC instruction set is based, and has a 32-bit Thumb ARM/16 SR double that call each other. Therefore, in order to improve code density and performance do not ask some of the Thumb instruction set code can be written.
Since the program small, low power consumption, interference and good, has been applied to complex electromagnetic environment of a vehicle communication equipment, the project meets the requirements of section CAN network points.